Master clock with electronic memory

ABSTRACT

A master clock having an oscillator, a divider, a signal shaper, an output amplifier, and power feed either by means of an electric circuit or by means of a battery at the time of power failure in the circuit. A detector for circuit voltage is provided which upon a fall in circuit voltage switches signals from the output of the divider to an electronic memory. Upon reestablishment of power in the circuit, the time signals are fed out of the memory at an accelerated rate to cause the secondary clocks controlled by the master clock to catch up. It is thus possible to use only a small and inexpensive standby battery for use during power failure.

United States Patent Marti et al.

[ June 17, 1975 1 1 MASTER CLOCK WITH ELECTRONIC MEMORY [75] Inventors: Raymond Marti, Meyrin, Geneva; Olivier Chanson, Avully, Geneva, both of Switzerland [73] Assignee: Patek Philippe S.A., Geneva, Switzerland [22] Filed: Oct. 19, 1973 [21] Appl. No.: 407,963

[52] US. Cl. H 58/25; 58/23 BA; 58/24 R [51] Int. Cl. G041: 1/00 [58] Field of Search 58/152 H, 24 R, 24 A, 25, 58/26 R, 26 B, 33, 23 R, 34, 35 R [56] References Cited UNITED STATES PATENTS 3,282,043 11/1966 Duris 58/24 R 3,643,420 2/1972 Haydon 58/24 R 3,690,059 9/1972 Haydon i. 58/24 R Primary ExaminerStephen .l. Tomsky Assistant Examiner-U. Weldon Attorney, Agent, or Firm-Young & Thompson 5 7 ABSTRACT A master clock having an oscillator, a divider, a signal shaper, an output amplifier, and power feed either by means of an electric circuit or by means of a battery at the time of power failure in the circuit. A detector for circuit voltage is provided which upon a fall in circuit voltage switches signals from the output of the divider to an electronic memory. Upon reestablishment of power in the circuit, the time signals are fed out of the memory at an accelerated rate to cause the secondary clocks controlled by the master clock to catch up, It is thus possible to use only a small and inexpensive standby battery for use during power failure,

1 MASTER CLOCK WITH ELECTRONIC MEMORY The present invention relates to a master clock with an electronic memory, which permits eliminating large and costly sealed accumulators which in the past have been necessary to control the secondary clocks in the event of power failure.

The master clock with an electronic memory according to the present invention comprises an oscillator, a divider, a signal shaper, and an output amplifier as well as circuit power supply and battery power supply, characterized in that it comprises also a circuit voltage detector, a memory and a logical device providing for commutation or switching of the divider output to the memory when the circuit voltage falls below a predetermined value, as well as the accelerated feedout of the accumulated signals in the memory upon reestablishment of the circuit.

The accompanying drawings show schematically and by way of example one embodiment of master clock according to the invention. In the drawings:

FIG. 1 is a block diagram of the master clock;

FIG. 2 is a circuit diagram thereof; and

FIG. 3 is a more detailed fragmentary circuit diagram of the voltage detector of the feed circuit.

The master clock comprises a time base or oscillator 1 that delivers a signal 1 to a frequency divider 2, 2a which one the one side delivers second signals s and on the other side minute signals m. These trains of signals are normally fed by a logic commutator circuit 3 to a signal shaper 4 which shapes the signals to actuate an output amplifier 5 which in turn controls secondary clocks 6 and 6a.

The master clock also comprises a power supply 7 from a distribution circuit 8 and a battery 9 which is continuously charged by circuit 8 and which feeds the various electronic components of the master clock, the secondary clocks being directly fed by the same or a different supply.

The master clock comprises also a detector 10 for the voltage of circuit 8, which controls the logic commutation circuit 3 so as to disconnect the signal shaper 4 and to divert the signals delivered by the divider 2, 2a to the memory 11 which is in the form of a known adding and subtracting counter.

The power feed is illustrated in greater detail in FIG. 3, as including the transformer 12 and double alternating rectifier 13 delivering feed current continuously to conductors a and b.

The voltage detector comprises a resistive voltage divider 14 and Zener diode feeding a logic gate 15. If the circuit is energized, the input to gate 15 is of positive potential. When the circuit voltage falls, the voltage falls at the input of gate 15 which switches at its threshhold voltage. A capacitor 16 renders the device independent of very rapid variations of voltage, whose origin for example may be parasitic. The switching of gage 15 controls the logic circuit of commutator 3.

Power supply 7 furnishes directly the current necessary for the amplifier 5. It also assures maintenance of the battery 9 in a charged condition, which battery alone will, in the case of power failure, feed the electronic circuits which consume not more than about several milliamperes. The battery 9 therefore may be small and relatively inexpensive.

The minute and second signal m and s delivered by the frequency divider 2, 2a are fed to the commutation circuit 3. In normal operation, when the circuit is feeding power, the minute signals are fed directly by m to the shaper 4 controlling the amplifier 5 which in turn controls the secondary clocks 6 and 6a.

if the circuit 8 fails or suffers a substantial voltage drop, the voltage detector 10 acts on the logic commutation circuit 3 which deactivates the signal shaper 4 and directs the minute signals by m" to the memory 11 where they are accumulated. This is the condition of the apparatus as shown in FIG. 1. Memory 11 as indicated above, is a bidirectional counter which in FIG. 1 is in the counting position.

When the power is restored, the logic commutation circuit 3 applies the signals s with accelerated frequency, on the one hand to signal shaper 4 through 5 and on the other hand to memory 11 through 3'', at which time the memory is in its subtractive or reverse counting position.

As soon as the logic commutator 3 detects that the memory 11 is empty, that is, has counted back to zero, it switches the direction of the shaper 4 through the normal minute signals m' and cuts off the memory.

Referring now to FIG. 2, which is more detailed as to the logic circuit of commutator 3, it will be seen that the frequency divider 2 delivers to the logic circuit 3, three distinct signals:

1. Minute signals m,-

2. Second signals (or other divisions of a minute) s; and

3. A warning 0 of an impending minute signal, that is, a preparatory signal that precedes the minute signal by a predetermined interval.

The detector 10 delivers a signal f indicatin g the presence or absence of power. Memory 11 delivers to the commutator circuit 3 a signal 1: when the memory is empty, that is, a memory empty" signal.

Logic circuit 3 delivers the necessary signals m, s and m", s" to the signal shaper 4 and to the memory 11, respectively.

Accordingly, three distinct conditions of operation of the apparatus may be distinguished:

l. Circuit 8 is powered, corresponding to normal operation of the master clock. The memory empty" signal x blocks the second signals s but lets pass the minute signals m. The power signal f opens the gate 16 of the shaper 4. The shaper 4 is therefore fed normally by the minute signals m. Eventually, a reset signal is applied to memory 11.

2. Circuit 8 has failed and the minute signals m are stored in the memory. Signal f indicates the absence of power in circuit 8 and cancels the reset signal r of memory 11 at the same time that it blocks the gate 16 of the shaper 4. This signal f also switches the memory to its counting position. When the memory has received and stored a signal, the memory empty signal 2: disappears. The counting of the minutes signals m" continues.

3. Circuit 8 is repowered and it is necessary for the secondary clocks to be advanced as they have not been actuated during the second phase of operation recited above. The power signal f reopens the gate of the shaper 4. The memory is placed in the reverse counting or subtracting position by the signal f. When the "memory empty signal at reappears, the second signals are switched through s to the shaper 4 and through s" to the memory, while the minute signals m are blocked.

The warning signal c is given during reverse counting of the memory and inhibits the registry of the minute signals in the memory. Finally, when the memory empty signal reappears, the operation again resumes as set forth in case 1 above.

There has thus been provided by the present invention a master clock with accelerated reset upon resumption of power following a power failure. which requires only a relatively small battery for power during the failure.

It will of course be understood that the components of the present invention that are not illustrated in detail may be entirely conventional and so do not require further elaboration.

Although the present invention has been described and illustrated in connection with a preferred embodiment, it is to be understood that modifications and variations may be resorted to without departing from the spirit of the invention. as those skilled in this art will readily understand. Such modifications and variations are considered to be within the purview and scope of the present invention as defined by the appended claims. 1

Having described our invention, we claim:

1. In a master clock comprising an oscillator, a divider connected to the output of said oscillator. a signal shaper, an output amplifier receiving signals from said signal shaper, and means to supply power to the clock from a power circuit through a battery to said oscillator and divider and shaper and directly to the rest of the clock; the improvement comprising a voltage detector for said circuit, a memory and a logic device receiving signals from the voltage detector and transmitting signals to said signal shaper, said logic device having means switching the output of the divider from the signal shaper to the memory when the circuit voltage falls below a predetermined value, said logic device also having means responsive to re-establishment of voltage in said circuit above said predetermined value to feed out signals stored in said memory to said signal shaper at a faster rate than their rate of storage.

2. A master clock as claimed in claim 1, said logic device also having means preventing feed out of signals from said memory at the time of passage of normal minute signals of the clock.

i l k l t 

1. In a master clock comprising an oscillator, a divider connected to the output of said oscillator, a signal shaper, an output amplifier receiving signals from said signal shaper, and means to supply power to the clock from a power circuit through a battery to said oscillator and divider and shaper and directly to the rest of the clock; the improvement comprising a voltage detector for said circuit, a memory and a logic device receiving signals from the voltage detector and transmitting signals to said signal shaper, said logic device having means switching the output of the divider from the signal shaper to the memory when the circuit voltage falls below a predetermined value, said logic device also having means responsive to re-establishment of voltage in said circuit above said predetermined value to feed out signals stored in said memory to said signal shaper at a faster rate than their rate of storage.
 2. A master clock as claimed in claim 1, said logic device also having means preventing feed out of signals from said memory at the time of passage of normal minute signals of the clock. 